1. Technical Field
Various embodiments generally relate to a sense amplifier and a semiconductor device including the same, and more particularly to a technology for securing the operation margin of a sense amplifier.
2. Related Art
Recent developments in electronic systems are leading to advances in highly integrated high-speed semiconductor memory devices. In order to increase the operating speeds of the semiconductor memory devices, a synchronous memory device has been developed. This synchronous memory device is a device that has an interface being synchronized with a system clock.
A single data rate (hereinafter, referred to as “SDR”) synchronous memory device usually refers to a synchronous memory device in which only one word of data is transmitted per clock cycle. In the SDR synchronous memory device, for example, the input and output of the data is in synchronization with the rising edge of a clock signal.
The next generation of synchronous memory device is double data rate (hereinafter, referred to as “DDR”) synchronous memory device. A DDR synchronous memory device usually refers to a synchronous memory device that reads or writes two words of data per clock cycle. The interface technology of the DDR synchronous memory device may be accomplished by reading and writing data on both the rising and falling edges of the clock signal.
This allows a doubling of bandwidth without having to change the frequency of the clock signal.
Among various semiconductor memory devices, a dynamic random access memory (hereinafter, referred to as “DRAM”) is a representative volatile memory. The memory cell of the DRAM may include a cell transistor and a cell capacitor.
The cell transistor allows a memory controller to control an access to the cell capacitor, which stores charges corresponding to data. That is to say, according to the amount of the charges stored in the cell capacitor, a sense amplifier may sense the amount of the charges to determine what the charges stored in the cell capacitor represent between a logic-high level and a logic-low level. If a word line is enabled in a semiconductor memory device, charge sharing occurs between a bit line and a bit line bar, and then the sense amplifier operates.
FIG. 1 illustrates that a logic-low data stored in a cell is driven by a pull-down control signal after a charge-sharing operation started. A sense amplifier senses the logic-low data of the cell through a pair of bit lines BL and BLB when a word line WL is enabled. FIG. 2 illustrates that a logic-high data stored in the cell is driven by a pull-up control signal after a charge-sharing operation started. The sense amplifier senses the logic-high data of the cell through the pair of bit lines BL and BLB when the word line WL is enabled.
However, continued advances in highly integrated DRAM are leading to a reduction in cell area, which may cause a decrease in capacitance of cell capacitors. As a consequence, a sensing margin Delta V may decrease as shown in FIGS. 1 and 2.